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innovative power tm - 1 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. rev 9, 15-nov-12 act8810 system blo ck diagram eight channel activepath tm power management ic features ? activepath tm li+ charger with system power selection ? six integrated regulators ? 1.3a high efficiency step-down dc/dc ? 1.0a high efficiency step-down dc/dc ? 0.55a high efficiency step-down dc/dc ? 2360ma low noise, high psrr ldos ? 30ma rtc ldo / backup battery charger ? i 2 c tm serial interface ? minimal external components ? compatible with usb or ac-adapter charging ? 5mm 5mm, thin-qfn (tqfn55-40) package ? only 0.75mm height ? rohs compliant applications ? personal navigation devices ? portable media players ? smart phones general description the patent-pending act8810 is a complete, cost effective, highly-efficient activepmu tm power management solution that is ideal for a wide range of high performance portable handheld applications such as personal navigation devices (pnds). this device integrates the activepath tm complete battery charging and management system with six power supply channels. the activepath architecture automatically selects the best available input supply for the system. if the external input source is not present or the system load current is more than the input source can provide, the activepath supplies additional current from the battery to the system. the charger is a complete, thermally- regulated, stand-alone single-cell linear li+ charger that incorporates an in ternal power mosfet. reg1, reg2, and reg3 are three independent, fixed-frequency, current-mode step-down dc/dc converters that output 1.3a, 1.0a, and 0.55a, respectively. reg4 and reg5 are high performance, low-noise, low-dropout linear regulators that output up to 360ma each. reg6 is a rtc ldo that outputs up to 30ma for a real time clock. finally, an i 2 c serial interface provi des programmability for the dc/dc converters and ldos. the act8810 is available in a tiny 5mm x 5mm 40- pin thin-qfn package that is just 0.75mm thin. out4 0.9v to 3.3v up to 360ma out3 adjustable, or 0.8v to 4.4v up to 0.55a system control out1 adjustable, or 0.8v to 4.4v up to 1.3a out5 0.9v to 3.3v up to 360ma nirq on1 on3 npbin activepath tm & single-cell li+ battery charger battery programmable up to 1a vsys chg_in chglev dccc out2 adjustable, or 0.8v to 4.4v up to 1.0a nstat1 acin nrsto scl sda vsel iset out6 0.9v to 3.3v up to 30ma reg6 rtc_ldo act8810 reg1 step-down dc/dc reg2 step-down dc/dc reg3 step-down dc/dc reg4 ldo reg5 ldo on2 th btr nstat0 pmu pmu pmu tm a ctive
act8810 rev 9, 15-nov-12 innovative power tm - 2 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. table of contents general info rmation .......................................................................................... p. 01 functional block diagram ...................................................................................................... p. 03 ordering information .......................................................................................................... .... p. 04 pin configuration ............................................................................................................. ....... p. 04 pin descriptions .............................................................................................................. ....... p. 05 absolute maximum ratings .................................................................................................... p. 07 system manag ement ........................................................................................... p. 08 register descriptions ......................................................................................................... .... p. 08 i 2 c interface electrical characteristics ................................................................................... p. 0 9 electrical characteristics .................................................................................................... .... p. 10 register descriptions ......................................................................................................... .... p. 11 typical performance characteristics ...................................................................................... p. 12 functional description ........................................................................................................ .... p. 13 step-down dc/dc converte rs .......................................................................... p. 17 electrical characteristics .................................................................................................... .... p. 17 typical performance characteristics ...................................................................................... p. 20 register descriptions ......................................................................................................... .... p. 22 functional description ........................................................................................................ .... p. 28 low-dropout line ar regula tors .................................................................. p. 31 electrical characteristics .................................................................................................... .... p. 31 typical performance characteristics ...................................................................................... p. 33 register descriptions ......................................................................................................... .... p. 34 functional description ........................................................................................................ .... p. 36 rtc low-dropout li near regu lator ............................................................ p. 37 electrical characteristics .................................................................................................... .... p. 37 register descriptions ......................................................................................................... .... p. 38 functional description ........................................................................................................ .... p. 39 activepath tm charger ............................................................................................. p. 40 electrical characteristics .................................................................................................... .... p. 40 typical performance characteristics ...................................................................................... p. 42 functional description ........................................................................................................ .... p. 44 package info rmation .......................................................................................... p. 53
act8810 rev 9, 15-nov-12 innovative power tm - 3 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. reg2 reg1 reg3 functional block diagram
act8810 rev 9, 15-nov-12 innovative power tm - 4 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. pin configuration ordering information top view thin - qfn (tqfn55-40) : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of haza rdous substances) standards. : to select v stbyx as a output regulation voltage of regx, tie vsel to vsys or a logic high. : refer to the control sequence section for more information. part number v out1 /v stby1 v out2 /v stby2 v out3 /v stby3 v out4 v out5 v out6 control sequence act8810qj1c1-t 3.3v/3.3v 1.1v/1.2v 1. 2v/1.2v 1.2v 2.8v 3.3v sequence a act8810qj213-t 1.2v/1.2v 1.8v/1.8v 1. 0v/1.0v 3.3v 1.2v 3.0v sequence b act8810qj3eb-t 3.3v/3.3v 1.2v/1.2v 1. 8v/1.8v 1.5v 2.8v 3.3v sequence c act8810qj420-t 3.3v/3.3v 1.8v/1.8v 1. 1v/1.2v 1.2v 3.3v 2.5v sequence d act8810qj50f-t 1.2v/1.2v 3.3v/3.3v 1. 8v/1.8v 3.3v 1.8v 3.0v sequence e th dccc chglev acin bat bat vsys vsys chg_in iset act8810 btr out5 vp3 sw3 gp3 out3 npbin sda scl on3 out6 out1 vp1 gp1 gp2 sw2 vp2 out2 on1 vsel sw1 nirq nrsto refbp ga on2 nstat0 out4 inl nstat1 ep packaging details package pins temperature range packing act8810qj###-t tqfn55-40 40 -40c to +85c tape & reel
act8810 rev 9, 15-nov-12 innovative power tm - 5 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. pin descriptions pin name description 1 th temperature sensing input. connect to battery thermist or. th is pulled up with a 100a current internally. see the battery temperature monitoring section for mo re information. 2 dccc dynamic charging current control. connect a resistor to set the dynamic charging current control point. a internal 100a current source sets up a voltage that is used to compare with vsys and dynamically scale the charging current to maintain vsys regulation. see the dynamic charge current control section for more information. 3 btr safety timer program pin. the resistance betwe en this pin and ga determines the timers timeout values. see the charging safety timers section for mo re information. 4 acin ac adaptor detect. detects presence of a wall adapt or and automatically ad justs the charge current to the maximum charge current level. do not leave acin floating. 5, 6 bat battery charger outpu t. connect this pin directly to the battery anode (+ terminal) 7, 8 vsys system output pin. bypass to ga with a 10f or lar ger ceramic capacitor. 9 chg_in power input for the battery charger. bypass chg_in to ga with a capacitor placed as close to the ic as possible. the battery charger are automat ically enabled when a valid voltage is present on chg_in. see the chg_in bypass capacitor selection section for mo re information. 10 iset charge current set. program the maximum c harge current by connecting a resistor (r iset ) between iset and ga. see the charger current programming section for mo re information. 11 vsel step-down dc/dcs output voltage sele ction. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. see the output voltage selection pin section for more information. 12 on1 independent enable control input for reg1. drive on1 to vsys or to a logic high for normal operation, drive to ga or a logic low to disable reg1. do not leave on1 floating. 13 out2 output feedback sense for reg2. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 14 vp2 power input for reg2. bypass to gp2 with a high quality ceramic capacitor placed as close as possible to the ic. 15 sw2 switching node output for reg2. connect th is pin to the switching end of the inductor. 16 gp2 power ground for reg2. connect ga, gp1, gp2 and gp 3 together at a single point as close to the ic as possible. 17 gp1 power ground for reg1. connect ga, gp1, gp2 and gp 3 together at a single point as close to the ic as possible. 18 sw1 switching node output for reg1. connect th is pin to the switching end of the inductor. 19 vp1 power input for reg1. bypass to gp1 with a high quality ceramic capacitor placed as close as possible to the ic. 20 out1 output feedback sense for reg1. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 21 on3 enable control input for reg3. drive on3 to a logi c high for normal operation, drive to ga or a logic low to disable reg3. do not leave on3 floating. 22 scl clock input for i 2 c serial interface. 23 sda data input for i 2 c serial interface. data is read on the rising edge of scl.
act8810 rev 9, 15-nov-12 innovative power tm - 6 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. pin descriptions cont?d pin name description 25 out3 output feedback sense for reg3. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 26 gp3 power ground for reg3. connect ga, gp1, gp2, and gp3 together at a single point as close to the ic as possible. 27 sw3 switching node output for reg3. connect th is pin to the switching end of the inductor. 28 vp3 power input for reg3. bypass to gp3 with a high quality ceramic capacitor placed as close as possible to the ic. 29 out6 rtc ldo output voltage. capable of delivering up to 30ma of output current. 30 out5 output voltage for reg5. capable of deliveri ng up to 360ma of output current. the output is discharged to ga with 1k ? when disabled. 31 inl power input for reg4, reg5, and reg6. bypass to ga with a high quality ceramic capacitor placed as close as possible to the ic. 32 out4 output voltage for reg4. capable of deliveri ng up to 360ma of output current. the output is discharged to ga with 1k ? when disabled. 33 nstat0 active-low open-drain charger status output. nstat0 has a 5ma (typ) current limit, allowing it to directly drive an indicator led without additional external components. to generate a logic-level output, connect nstat0 to an appropriate supply voltage (typically vsys) through a 10k ? or greater pull-up resistor. see the charge status indication section for more information. 34 on2 independent enable control input for reg2. drive on 2 to a logic high for normal operation, drive to ga or a logic low to disable reg2. do not leave on2 floating. 35 ga analog ground. connect ga directly to a quiet ground node. connect ga, gp1, gp2, and gp3 together at a single point as close to the ic as possible. 36 refbp reference noise bypass. connect a 0.01 f ceramic capacitor from re fbp to ga. this pin is discharged to ga in shutdown. 38 nrsto open-drain reset output. nrsto asserts low whenev er reg1 is out of regulation, and remains low for 260ms (typ) after reg1 reaches regulation. 39 nirq open-drain interrupt output. nirq asserts any time npbin is asserted or an unmasked fault condition exists. see the nirq output section for more information. 40 chglev charging state select input. when acin = 0 charge current is internally set; dr ive chglev to a logic-high for high-current usb charging mode (maximum charge current is 500ma), drive chglev to a logic-low for low-current usb charging mode (maximum charge current is 100ma). when acin = 1 charge current is externally set by r iset ; drive chglev to a logic-high to for high- current charging mode (iset (ma) = k iset 1v/(r iset (k ? ) +0.031) where k iset = 628), drive chglev to a logic-low for low-current charging mode (iset (ma) = k iset 1v/(r iset (k ? ) + 0.031) where k iset = 314). do not leave chglev floating. ep ep exposed pad. must be soldered to ground on the pcb. 24 npbin master enable input. drive npbin to ga through a 100k ? resistor to enable the ic, drive npbin directly to ga to assert a ha rd-reset condition. refer to the system startup & shutdown and control sequence sections for more information. npbin is internally pulled up to vsys through a 50k ? resistor. 37 nstat1 active-low open-drain charger status output. nstat1 has a 5ma (typ) current limit, allowing it to directly drive an indicator led without additional external components. to generate a logic-level output, connect nstat1 to an appropriate supply voltage (typically vsys) through a 10k ? or greater pull-up resistor. see the charge status indication section for more information.
act8810 rev 9, 15-nov-12 innovative power tm - 7 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. absolute maximum ratings parameter value unit chg_in to ga t < 1ms and duty cycle <1% steady state -0.3 to +18 -0.3 to +14 v v vp1 to gp1, vp2 to gp2, vp3 to gp3 -0.3 to +6 v bat, vsys, inl to ga -0.3 to +6 v sw1, out1 to gp1 -0.3 to (v vp1 +0.3) v sw2, out2 to gp2 -0.3 to (v vp2 +0.3) v sw3, out3 to gp3 -0.3 to (v vp3 +0.3) v operating ambient temper ature -40 to 85 c maximum junction temperature 125 c maximum power dissipation tqfn55-40 (thermal resistance ja = 30 o c/w) 2.7 w storage temperature -65 to 150 c lead temperature (soldering, 10 sec) 300 c on1, on2, on3, iset, acin, vsel, dccc, chglev, th, scl, sd a, refbp, nirq, nrsto, nstat0, nstat1, btr, npbin to ga -0.3 to +6 v out4, out5, out6 to ga -0.3 to (v inl +0.3) v : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability.
system management act8810 rev 9, 15-nov-12 innovative power tm - 8 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. key: r: read-only bits. no default assigned. v: default values depend on voltage option. default values may vary. note: addresses other than those specified in table 1 may be used for factory settings. do not access any registers other than those specified in table 1. register descriptions table 1: global register map output address data (default value) hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sys 06h 0 0 0 0 0 1 1 0 r r r 0 r r 1 r reg1 10h 0 0 0 1 0 0 0 0 r r v v v v v v reg1 11h 0 0 0 1 0 0 0 1 r r r r r r r r reg1 12h 0 0 0 1 0 0 1 0 r r r r r 0 r 1 reg1 13h 0 0 0 1 0 0 1 1 r v v v v v v v reg2 20h 0 0 1 0 0 0 0 0 r r v v v v v v reg2 21h 0 0 1 0 0 0 0 1 r r r r r r r r reg2 22h 0 0 1 0 0 0 1 0 r r r r r 0 r 1 reg2 23h 0 0 1 0 0 0 1 1 r v v v v v v v reg3 30h 0 0 1 1 0 0 0 0 r r v v v v v v reg3 31h 0 0 1 1 0 0 0 1 r r r r r r r r reg3 32h 0 0 1 1 0 0 1 0 r r r r r 0 r 1 reg3 33h 0 0 1 1 0 0 1 1 r v v v v v v v reg4 40h 0 1 0 0 0 0 0 0 1 r 1 v v v v v reg4 43h 0 1 0 0 0 0 1 1 r r r r r r 0 r reg5 41h 0 1 0 0 0 0 0 1 1 r 1 v v v v v reg6 42h 0 1 0 0 0 0 1 0 r r r v v v v v
system management act8810 rev 9, 15-nov-12 innovative power tm - 9 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. i 2 c interface electrical characteristics figure 1: i 2 c serial bus timing (v vsys = 3.6v, t a = 25c, unless otherwise specified.) scl sda in sda out t sp t hd t st t su t scl parameter test conditions min typ max unit scl, sda low input voltage v vsys = 2.6v to 5.5v, t a = -40oc to 85oc 0.35 v scl, sda high input voltage v vsys = 2.6v to 5.5v, t a = -40oc to 85oc 1.55 v scl, sda leakage current 1 a sda low output voltage i ol = 5ma 0.3 v scl clock period, t scl 2.5 s sda data in setup time to scl high, t su 100 ns sda data out hold time after scl low, t hd 300 ns sda data low setup time to scl low, t st start condition 100 ns sda data high hold time after clock high, t sp stop condition 100 ns
system management act8810 rev 9, 15-nov-12 innovative power tm - 10 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. electrical characteristics (v vsys = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit input voltage range 2.6 5.5 v uvlo threshold voltage vsys rising 2.35 2.5 2.6 v uvlo hysteresis vsys falling 100 mv vsys supply current onx = vsys 70 a vsys shutdown current onx = ga , not charging 30 a voltage reference 1.24 1.25 1.26 v oscillator frequency 1.35 1.6 1.85 mhz logic high input voltage on1, on2, on3, vsel 1.4 v logic low input voltage on1, on2, on3, vsel 0.4 v leakage current v on1 = v on2 = v on3 = v vsel = v nirq = v nrsto = 4v 1 a npbin internal pull-up resistance 50 k ? low level output voltage nirq, nrsto. sinking 10ma 0.3 v thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis te mperature decreasing 20 c nrsto delay 260 ms
system management act8810 rev 9, 15-nov-12 innovative power tm - 11 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions note: see table 1 for default register settings. table 2: control register map address data d7 d6 d5 d4 d3 d2 d1 d0 06h r r r w/e r r npbmask pbstat address name bit access fu nction description 06h pbstat [0] r/w push button status 0 de-assert 1 asserted 06h npbmask [1] r/w push button interrupt mask option 0 masked 1 not mask 06h [3:2] r read only 06h [4] w/e 06h [7:5] r read only write-exact table 3: control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written exac tly as specified in table 1.
system management act8810 rev 9, 15-nov-12 innovative power tm - 12 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. typical performanc e characteristics (v vsys = 3.6v, t a = 25c, unless otherwise specified.) shutdown current (a) temperature (c) 26 85 20 shutdown current vs. temperature act8810-002 -20 0 20 40 60 24 22 oscillator frequency vs. temperature oscillator frequency (mhz) temperature (c) 1.71 1.50 act8810-001 1.68 1.65 1.62 1.59 1.56 1.53 85 -20 0 20 40 60 on1 = on2 = on3 = ga v vsys = 4.2v v vsys = 3.6v v vsys = 3.2v -40 -40
system management act8810 rev 9, 15-nov-12 innovative power tm - 13 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description general description the act8810 offers a wide array of system management functions that allow it to be configured for optimal performance in a wide range of applications. i 2 c serial interface at the core of the act8810? s flexible architecture is an i 2 c interface that permits optional programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the act8810 uses standard i 2 c commands; i 2 c write-byte commands are used to program the act8810, and i 2 c read-byte commands are used to read the act8810?s internal registers. the act8810 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1011010x]. sda is a bi-directional data line and scl is a clock input. the master initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8-bit packets, beginning with the msb, and is clocked-in on the rising edge of scl. each packet of data is followed by an ?acknowledge? (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2-wire serial interface, go to the nxp website: http://www.nxp.com system startup and shutdown startup sequence the act8810 features a flexible enable architecture that allows it to support a variety of push-button enable/disable schemes. although other startup routines are possible, act8810 provides three typical startup and shutdown processes proceed as shown in control sequence section. shutdown sequence once a successful power-up routine is completed, a shutdown process may be initiated by asserting npbin a second time, typically as the result of pressing the push-button. although the shutdown process is completely softw are-controlled, a typical shutdown sequence proceeds as follows: the second assertion of n pbin asserts npbin and interrupts the microprocessor, which then initiates an interrupt service routine to reveal that npbin has been asserted. if there is no input to the charger, then the microprocessor disables each regulator according to the sequencing requirements of the system, then the system will finally be disabled when each of on1, on2, and on3 have been de- asserted. npbin input act8810's npbin pin is a dual-function pin, combining system enable/disable control with a hardware reset function. refering to figure 2, the two pin functions are obtained by asserting this pin low, either through a direct connection or through a 100k ? resistor, as described below. in most applications, npbin will be driven through a 100k ? resistor. when driven in this way, npbin initiates system startup or shutdown, as described in the system start up and shutdown section. when a hardware-reset function is desired, npbin may also be driven directly to ga. in this case, nrsto is immediately asserted low and remains low until npbin is de-asserted and the reset timeout period expires. this provides a hardware-reset function, allowing the system to be manually reset if the system processor locks up. although a typical application will use momentary switches to drive npbin, as shown in figure 2, npbin may also be driven by other sources, such as a gpio or other logic output. figure 2: npbin input enable/disable inputs (on1, on2 and on3) the act8810 provides three manual enable/disable inputs, on1, on2 and on3, which
system management act8810 rev 9, 15-nov-12 innovative power tm - 14 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. enable and disable reg1, reg2, and reg3, respectively. once the system is enabled, the system will remain enabled until all of on1, on2, and on3 have been de-asserted. see the control sequence section for more information. power-on reset output nrsto is an open-drain output which asserts low upon startup or when npbin is driven directly to ga, and remains asserted low until the 260ms (default) power-on reset timer has expired. connect a 10k ? or greater pull-up resistor from nrsto to an appropriate voltage supply. nirq output nirq is an open-drain output that asserts low any time startup or an unmasked fault condition exists. when asserted, nirq remains low until the microprocessor polls the act8810's i 2 c interface. the act8810 supports a variety of other fault conditions, which may each be optionally unmasked via the i 2 c interface. for more information about the available fault conditions, refer to the appropriate sections of this datasheet. connect a pull-up resistor from nirq to an appropriate voltage supply. ni rq is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. thermal shutdown the act8810 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the act8810 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). control sequence sequence a the act8810qj1## which is set with ?sequence a?, has a system startup is initiated whenever the following conditions occurs: 1) npbin is pushed low via 100k ? resistance, when ever this condition exists, the act8810qj1## begins its system startup procedure by enabling reg1. when reg1 reaches 94% of its final regulation voltage, act8810qj1## automatically turns on reg4 and reg5 and nrsto is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. if v out1 is within 6% of its regulation voltage when the reset timer expires, the nrsto is de-asserted, and the microprocessor can begin its power-up sequence. once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asse rts any one of on1, on2 or on3, and reg4, reg5 may be enabled or disabled via the i 2 c interface. this start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of on1, on2, and on3), providing protection against inadvertent momentary assertions of the pushbutton. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional time delay before asserting on1, on2, or on3. if the microprocessor is unable to complete its power-up routine successfu lly before the user lets go of the push-button, the act8810qj1## automatically shuts itself down. figure 3: sequence a functional description cont?d 260ms 94% of v out1 npbin system enable out1 out2, out3 reset time enable nrsto first push button assert power-hold second push button release button system shutdown on1, on2, on3 out4, out5 nirq
system management act8810 rev 9, 15-nov-12 innovative power tm - 15 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. system shutdown 260ms 94% of v out1 npbin system enable out1 enable qualification out2, out3 reset time enable nrsto ~100ms first push button assert power-hold second push button release button on1, on2, on3 out4, out5 reg4.on[ ], reg5.on[ ] nirq 260ms 94% of v out1 npbin system enable out1 enable qualification out2, out3 reset time enable nrsto ~100ms first push button assert power-hold second push button release button system shutdown on1, on2, on3 out4, out5 nirq sequence b the act8810qj2## which is set with ?sequence b?, has a system startup is initiated whenever the following conditions occurs: 1) npbin is pushed low via 100k ? resistance, when ever this condition exists, the act8810qj2## begins its system startup procedure by enabling reg1. when reg1 reaches 94% of its final regulation voltage, act8810qj2## automatically turns on reg2 and reg3 and nrsto is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. if v out1 is within 6% of its regulation voltage when the reset timer expires, the nrsto is de-asserted, and the microprocessor can begin its power-up sequence. once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asse rts any one of on1, on2 or on3. reg4 and reg5 may be enabled if the microprocessor sets reg4.on[ ] and reg5.on[ ] to 1 via the i 2 c interface. in other case, reg4 and reg5 are disable. this start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of on1, on2, and on3), providing protection against inadvertent momentary assertions of the pushbutton. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional time delay before asserting on1, on2, or on3. if the microprocessor is unable to complete its power-up routine successfu lly before the user lets go of the push-button, the act8810qj2## automatically shuts itself down. figure 4: sequence b sequence c the act8810qj3## which is set with ?sequence c?, has a system startup is initiated whenever the following conditions occurs: 1) npbin is pushed low via 100k ? resistance, when ever this condition exists, the act8810qj3## begins its system startup procedure by enabling reg1. when reg1 reaches 94% of its final regulation voltage, act8810qj3## automatically turns on reg2, reg3, reg4, reg5 and nrsto is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. if v out1 is within 6% of its regulation voltage when the reset timer expires, the nrsto is de-asserted, and the microprocessor can begin its power-up sequence. once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microproc essor asserts any one of on1, on2 or on3, and reg4, reg5 may be enabled or disabled via the i 2 c interface. this start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of on1, on2, and on3), providing protection against inadvertent momentary assertions of the pushbutton. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional time delay before asserting on1, on2, or on3. if the microprocessor is unable to complete its power-up routine successfu lly before the user lets go of the push-button, the act8810qj3## automatically shuts itself down. figure 5: sequence c
system management act8810 rev 9, 15-nov-12 innovative power tm - 16 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. sequence d the act8810qj4## which is set with ?sequence d?, has a system startup is initiated whenever the following condition occurs: 1) npbin is pushed low via 100k ? resistance, when ever this condition exists, the act8810qj4## begins its system startup procedure by enabling reg1, when reg1 reaches 94% of its final regulation voltage, act8810qj4## automatically turns on reg2, reg4, reg5 and nrsto is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. when the reset timer expires, the nrsto is de- asserted and the microp rocessor can begin its power-up sequence. once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of on1, on2 or on3, holding reg1, reg2, reg4, reg5, and enabling reg3. and any regulators could be enabled or disabled via the i 2 c interface. this start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of on1, on2, and on3), providing protection against inadvertent momentary assertions of the pushbutton. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional time delay before asserting on1, on2, or on3. if the microprocessor is unable to complete its power-up routine successfu lly before the user lets go of the push-button, the act8810qj4## automatically shuts itself down. figure 6: sequence d sequence e the act8810qj5## which is set with ?sequence e?, has a system startup is initiated whenever the following conditions occurs: 1) a valid input voltage is present at vin, or 2) npbin is pushed low via 100k ? resistance, when ever this condition exists, the act8810qj5## begins its system startup procedure by enabling reg1. when reg1 reaches 94% of its final regulation voltage, act8810qj5## automatically turns on reg2, reg3, reg4, reg5 and nrsto is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. if v out1 is within 6% of its regulation voltage when the reset timer expires, the nrsto is de-asserted, and the microprocessor can begin its power-up sequence. once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of on1, on2 or on3, and reg4, reg5 may be enabled or disabled via the i 2 c interface. this start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of on1, on2, and on3), providing protection against inadvertent momentary assertions of the pushbutton. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional time delay before asserting on1, on2, or on3. if the microprocessor is unable to complete its power-up routine successfu lly before the user lets go of the push-button or un-plug charger input, the act8810qj5## automatically shuts itself down. figure 7: sequence e 260ms npbin system enable out1 out3 reset time enable nrsto first push button assert power-hold second push button release button system shutdown on1, on2, on3 nirq out2, out4, out5 94% of v out1 260ms 94% of v out1 npbin system enable out1 enable qualification reset time enable nrsto ~100ms first push button assert power-hold second push button release button system shutdown on1, on2, on3 out2, out3 nirq chg_in or out4, out5
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 17 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. (v vsys = 3.6v, t a = 25c, unless otherwise specified.) : v nom1 refers to the nominal output voltage level for v out1 as defined by the ordering information section. electrical characteristics (reg1) parameter test conditions min typ max unit vp1 operating voltage range 2.9 5.5 v vp1 uvlo threshold input vo ltage rising 2.7 2.8 2.9 v vp1 uvlo hysteresis input voltage falling 85 mv quiescent supply current 130 200 a shutdown supply current reg1 is disabled, v vp1 = 4.2v 0.1 1 a output voltage accuracy v nom1 < 1.5v, i out1 = 10ma -2.1% v nom1 +2.1% v nom1 1.5v, i out1 = 10ma -1.5% v nom1 +1.5% line regulation v vp1 = max(v nom1 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out1 = 10ma to 1.3a 0.0017 %/ma current limit 1.4 1.8 a oscillator frequency v out1 20% of v nom1 1.35 1.6 1.85 mhz v out1 = 0v 540 khz pmos on-resistance i sw1 = -100ma 0.16 0.24 ? nmos on-resistance i sw1 = 100ma 0.16 0.24 ? sw1 leakage current v vp1 = 5.5v, v sw1 = 5.5v or 0v 1 a power good threshold 94 %v nom1 minimum on-time 60 ns v
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 18 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. : v nom2 refers to the nominal output voltage level for v out2 as defined by the ordering information section. electrical characteristics (reg2) (v vsys = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit vp2 operating voltage range 2.9 5.5 v vp2 uvlo threshold input vo ltage rising 2.7 2.8 2.9 v vp2 uvlo hysteresis input voltage falling 85 mv quiescent supply current 130 200 a shutdown supply current reg2 disabled, v vp2 = 4.2v 0.1 1 a output voltage regulation accuracy v nom2 < 1.5v, i out2 = 10ma -2.1% v nom2 +2.1% v nom2 1.5v, i out2 = 10ma -1.5% v nom2 +1.5% line regulation v vp2 = max(v nom2 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out2 = 10ma to 1.0a 0.0017 %/ma current limit 1.15 1.45 a oscillator frequency v out2 20% of v nom2 1.35 1.6 1.85 mhz v out2 = 0v 540 khz pmos on-resistance i sw2 = -100ma 0.25 0.38 ? nmos on-resistance i sw2 = 100ma 0.17 0.26 ? sw2 leakage current v vp2 = 5.5v, v sw2 = 5.5v or 0v 1 a power good threshold 94 %v nom2 minimum on-time 60 ns v
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 19 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. : v nom3 refers to the nominal output voltage level for v out3 as defined by the ordering information section. electrical characteristics (reg3) (v vsys = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit vp3 operating voltage range 2.9 5.5 v vp3 uvlo threshold input vo ltage rising 2.7 2.8 2.9 v vp3 uvlo hysteresis input voltage falling 85 mv quiescent supply current 130 200 a shutdown supply current reg3 disabled, v vp3 = 4.2v 0.1 1 a output voltage regulation accuracy v nom3 < 1.5v, i out3 = 10ma -2.1% v nom3 +2.1% v nom3 1.5v, i out3 = 10ma -1.5% v nom3 +1.5% line regulation v vp3 = max(v nom3 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out3 = 10ma to 550ma 0.0017 %/ma current limit 0.55 0.7 a oscillator frequency v out3 20% of v nom3 1.35 1.6 1.85 mhz v out3 = 0v 540 khz pmos on-resistance i sw3 = -100ma 0.46 0.69 ? nmos on-resistance i sw3 = 100ma 0.3 0.55 ? sw3 leakage current v vp3 = 5.5v, v sw3 = 5.5v or 0v 1 a power good threshold 94 %v nom3 minimum on-time 60 ns v
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 20 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. vp2 input voltage (v) (act8810qj3eb, v vp1 = v vp2 = 3.6v, l = 3.3h, c vp1 = c vp2 = 4.7 f, c out1 = 22f, c out2 = 10 f, t a = 25c, unless otherwise specified.) typical performanc e characteristics reg1 r dson vs. vp1 input voltage reg1 r dson (m ? ) vp1 input voltage (v) 0 act8810-007 6.5 6.0 5.5 5.0 4.5 4.0 3.5 0.18 0.16 0.12 0.08 0.04 pmos nmos reg2 r dson vs. vp2 input voltage act8810-008 reg2 r dson (m ? ) 0 0.5 0.3 0.4 0.2 0.1 4.5 4.0 3.5 3.0 pmos nmos reg2 efficiency vs. load current reg2 efficiency (%) 100 1000 load current (ma) act8810-004 80 60 40 20 10 100 v out2 = 1.2v 0 1 reg1 efficiency vs. load current reg1 efficiency (%) 100 0 2 2000 load current (ma) act8810-003 80 60 40 20 20 200 v out1 = 3.3v v vsys = 4.2v v vsys = 3.6v 0.14 0.10 0.06 0.02 v vsys = 4.6v v vsys = 5.2v v vsys = 3.6v v vsys = 4.2v v vsys = 4.6v v vsys = 5.2v 5.0 5.5 6.0 out1 regulation voltage vs. temperature out2 regulation voltage (v) 3.318 3.282 temperature (c) -20 -40 0 20 40 60 3.315 3.312 3.309 3.306 3.303 3.300 3.297 3.294 3.291 3.288 3.285 85 i out1 = 35ma act8810-005 out2 regulation voltage vs. temperature out3 regulation voltage (v) 1.212 1.188 temperature (c) act8810-006 -20 -40 0 20 40 60 1.208 1.204 1.200 1.196 1.192 i out2 = 35ma 85
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 21 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. (act8810qj3eb, v vp3 = 3.6v, l = 3.3h, c vp3 = 4.7 f, c out3 = 10 f, t a = 25c, unless otherwise specified.) typical performance ch aracteristics cont?d out3 regulation voltage vs. tempera- out1 regulation voltage (v) 1.812 1.788 temperature (c) act8810-010 -20 -40 0 20 40 60 1.808 1.804 1.800 1.796 1.792 i out3 = 35ma 85 reg3 r dson (m ? ) vp3 input voltage (v) 6.0 0.1 reg3 r dson vs. vp3 input voltage act8810-011 0.45 0.35 0.25 0.50 0.40 0.30 0.20 0.15 5.0 4.5 4.0 3.5 3.0 pmos nmos reg3 efficiency vs. load current reg3 efficiency (%) 1000 load current (ma) act8810-009 80 10 100 v vsys = 4.2v v out3 = 1.2v 60 40 20 1 0 100 v vsys = 3.6v v vsys = 4.6v 5.5
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 22 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 10h r r 11h r r r r r r r r 12h r r r r r nfltmsk ok on 13h r vrange vset0 vset1 note: see table 1 for default register settings. table 4: reg1 control register map table 5: reg1 control register bit descriptions r: read-only bits. default values may vary. address name bit access fu nction description 10h vset1 [5:0] r/w reg1 standby out put voltage selection see table 4 10h [7:6] r read only 11h [7:0] r read only 12h on [0] r/w reg1 enable 0 reg1 disable 1 reg1 enable 12h ok [1] r reg1 power-ok 0 output is not ok 1 output is ok nfltmsk [2] r/w reg1 output voltage fault mask option 0 masked 1 not mask 12h [7:3] r read only 13h vset0 [5:0] r/w reg1 output voltage selection see table 4 13h vrange [6] r/w reg1 voltage range 0 min v out = 0.8v 1 min v out = 1.25v 13h [7] r read only 12h
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 23 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions cont?d table 6: reg1/vsetx[ ] output voltage setting reg1/vsetx[3:0] reg1/vsetx[5:4] reg1/vrange[ ] = [0] reg1/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 adjustable 1.025 1.425 1.825 adjust able 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : care must be taken when adjusting the vrange[ ] selection at address 13h bit-6 to avoid undesired output voltage selections. the vrange bit allows selection of the two output voltage rang es available for reg1, reg2 and reg3 (vrange = 0 ? v out range 0.8v to 2.2v, vrange = 1 ? v out range 1.3v to 4.4v). it is recommended that the user first establishes if the new v out voltage is within the current selected voltage range (selected by vrange) prior to changing the value of the vrange bit. : refer to the output voltage programming section for more information.
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 24 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 20h r r 21h r r r r r r r r 22h r r r r r nfltmsk ok on 23h r vrange vset0 vset1 note: see table 1 for default register settings. table 7: reg2 control register map table 8: reg2 control register bit descriptions r: read-only bits. default values may vary. address name bit access fu nction description 20h vset1 [5:0] r/w reg2 standby out put voltage selection see table 7 20h [7:6] r read only 21h [7:0] r read only 22h on [0] r/w reg2 enable 0 reg2 disable 1 reg2 enable 22h ok [1] r reg2 power-ok 0 output is not ok 1 output is ok nfltmsk [2] r/w reg2 output voltage fault mask option 0 masked 1 not mask 22h [7:3] r read only 23h vset0 [5:0] r/w reg2 output voltage selection see table 7 23h vrange [6] r/w reg2 voltage range 0 min v out = 0.8v 1 min v out = 1.25v 23h [7] r read only 22h
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 25 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions cont?d table 9: reg2/vsetx[ ] output voltage setting reg2/vsetx[3:0] reg2/vsetx[5:4] reg2/vrange[ ] = [0] reg2/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 adjustable 1.025 1.425 1.825 adjust able 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : care must be taken when adjusting the vrange[ ] selection at address 23h bit-6 to avoid undesired output voltage selections. the vrange bit allows selection of the two output voltage rang es available for reg1, reg2 and reg3 (vrange = 0 ? v out range 0.8v to 2.2v, vrange = 1 ? v out range 1.3v to 4.4v). it is recommended that the user first establishes if the new v out voltage is within the current selected voltage range (selected by vrange) prior to changing the value of the vrange bit. : refer to the output voltage programming section for more information.
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 26 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 30h r r 31h r r r r r r r r 32h r r r r r nfltmsk ok on 33h r vrange vset0 vset1 address name bit access fu nction description 30h vset1 [5:0] r/w reg3 standby out put voltage selection see table 10 30h [7:6] r read only 31h [7:0] r read only 32h on [0] r/w reg3 enable 0 reg3 disable 1 reg3 enable 32h ok [1] r reg3 power-ok 0 output is not ok 1 output is ok nfltmsk [2] r/w reg3 output voltage fault mask option 0 masked 1 not mask 32h [7:3] r read only 33h vset0 [5:0] r/w reg3 output voltage selection see table 10 33h vrange [6] r/w reg3 voltage range 0 min v out = 0.8v 1 min v out = 1.25v 33h [7] r read only 32h note: see table 1 for default register settings. table 10: reg3 control register map table 11: reg3 control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written ex actly as specified in table 1
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 27 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions cont?d table 12: reg3/vsetx[ ] output voltage setting reg3/vsetx[3:0] reg3/vsetx[5:4] reg3/vrange[ ] = [0] reg3/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 adjustable 1.025 1.425 1.825 adjust able 2.050 2.850 3.650 0001 0.800 1.050 1.450 1.850 1.300 2.100 2.900 3.700 0010 0.800 1.075 1.480 1.875 1.350 2.150 2.950 3.750 0011 0.800 1.100 1.500 1.900 1.400 2.200 3.000 3.800 0100 0.800 1.125 1.525 1.925 1.450 2.250 3.050 3.850 0101 0.800 1.150 1.550 1.950 1.500 2.300 3.100 3.900 0110 0.800 1.175 1.575 1.975 1.550 2.350 3.150 3.950 0111 0.800 1.200 1.600 2.000 1.600 2.400 3.200 4.000 1000 0.825 1.225 1.625 2.025 1.650 2.450 3.250 4.050 1001 0.850 1.250 1.650 2.050 1.700 2.500 3.300 4.100 1010 0.875 1.275 1.675 2.075 1.750 2.550 3.350 4.150 1011 0.900 1.300 1.700 2.100 1.800 2.600 3.400 4.200 1100 0.925 1.325 1.725 2.125 1.850 2.650 3.450 4.250 1101 0.950 1.350 1.750 2.150 1.900 2.700 3.500 4.300 1110 0.975 1.375 1.775 2.175 1.950 2.750 3.550 4.350 1111 1.000 1.400 1.800 2.200 2.000 2.800 3.600 4.400 : care must be taken when adjusting the vrange[ ] selection at address 33h bit-6 to avoid undesired output voltage selections. the vrange bit allows selection of the two output voltage rang es available for reg1, reg2 and reg3 (vrange = 0 ? v out range 0.8v to 2.2v, vrange = 1 ? v out range 1.3v to 4.4v). it is recommended that the user first establishes if the new v out voltage is within the current selected voltage range (selected by vrange) prior to changing the value of the vrange bit. : refer to the output voltage programming section for more information.
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 28 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description general description reg1, reg2, and reg3 are fixed-frequency, current-mode, synchronous pwm step-down converters that are capable of supplying up to 1.3a, 1.0a, and 0.55a of output current, respectively. these regulators operate with a fixed frequency of 1.6mhz, minimizing noise in sensitive applications and allowing the use of small external components, and achieve peak efficiencies of up to 97%. each step-down dc/dc is available with a variety of standard and custom output voltages, which may be software-controlled by systems requiring advanced power management functions, via the i 2 c interface. buck regulator pfm/pwm operating modes the buck converters offer pfm/pwm operating modes to maximize efficiency under both light and full load conditions. the device will automatically transition from fixed frequency pwm mode to pfm mode when the output current is approximately 100ma. in pfm mode, the device maintains output voltage regulation by adjusting the switching frequency. the device transitions into fixed frequency pwm mode when the output current reaches approximately 100ma. 100% duty cycle operation reg1, reg2 and reg3 are each capable of operating at up to 100% duty cycle. during 100% duty-cycle operation, the high-side power mosfet is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. synchronous rectification reg1, reg2 and reg3 eac h feature integrated channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the nee d for external rectifiers. enabling and disabling reg1, reg2 and reg3 reg1, reg2, and reg3 are typically enabled and disabled using the act8810's closed-loop enable/disable control scheme, including the npbin input. refer to the system startup and shutdown section for more information about this function. each regulator is enabled when the following conditions are met: 1) onx is asserted high to enable regx, 2) regx/onx[ ] is set to 1 when onx is high in addition reg1, reg2, or reg3 may be enabled when npbin is pushed low via 100k ? resistance. it depends on sequence is set. see the control sequence section for more information. when none of these conditions are true, reg1, reg2 and reg3 are disabled, and each regulator?s quiescent supply current drops to less than 1 a. power-ok reg1, reg2 and reg3 each feature a variety of status bits that can be read by the system microprocessor. if any output falls below its power- ok threshold, typically 6% below the programmed regulation voltage, regx/ok[ ] is cleared to 0. soft-start reg1, reg2 and reg3 each include matched soft-start circuitry. when enabled, the output voltages track the internal 80 s soft-start ramp and both power up in a monotonic manner that is independent of loading on either output. this circuitry ensures that each output powers up in a controlled manner, greatly simplifying power sequencing design considerations. compensation reg1, reg2 and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. no compensation design is required; simply follow a few simp le guide lines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 4.7 f ceramic capacitor for each of reg1, reg2 and reg3 is recommended for most applications. output capacitor selection for most applications, 22 f ceramic output capacitors are recommended for reg1 and 10 f ceramic output capacitors are recommended for reg2, reg3. although the these regulators were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr, low-esr tantalum capacitors can provide acceptable results as well.
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 29 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. (2) 1 fb 6 ff r 10 2 . 2 c ? = inductor selection reg1, reg2 and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. reg1, reg2 and reg3 of the device were optimized for operation with and 3.3 h inductor, although inductors in the 2.2 h to 4.7 h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current of the application by at least 30%. output voltage programming by default, reg1, reg2 and reg3 each power up and regulate to their default output voltage, as defined in the ordering information section. once the system is enabled, each regulator?s output voltage may be modified through either the i 2 c interface or the voltage selection (vsel) pin. programming via the i 2 c interface following startup, reg1, reg2, and reg3 may be independently programmed to different values by writing to the regx/vsetx[ _ ] and regx/vrange[ _ ] registers via the i 2 c interface. to program each regulator, first select the desired output voltage range via the regx/vrange[ ] bit. each regulator supports two overlapping ranges; set regx/vrange[ _ ] to 0 for voltages below 2.245v, set regx/vrange[ _ ] to 1 for voltages above 1.25v. once the desired range has been selected, program the output to a voltage within that range by setting the regx/vsetx bits. for more information about the output voltage setting options, refer to tables 4, 7, and 10, for reg1, reg2, and reg3, respectively. programming with adjustable option figure 8 shows the feedbac k network necessary to set the output voltage when using the adjustable output voltage option. se lect components as follows: set r fb2 = 51k ? , then calculate r fb1 using the following equation: where v fbx is 0.625v when regx vrange[ ] = 0 and 1.25v when regx vrange[ ] = 1 figure 8: output voltage programming finally choose c ff using the following equation: where r fb1 = 47k ? , use 47pf. when using adjustable option, outx pins works as fbx function. output voltage selection pin (vsel) act8810's vsel pin provides a simple means of alternating between two preset output voltage settings, such as may be needed for dynamic voltage selection (dvs). the operation of this pin is as follows: when vsel is driven to ga or a logic low, the output voltages of reg1, reg2, and reg3 are each defined by their vset0[ ] register. when vsel is driven to vsys or a logic high, the output voltages of reg1, reg2, and reg3 are each defined by their vset1[ ] register. by default, each regulator's vset0[ ] and vset1[ ] registers are both programm ed to the same voltage, as defined in the ordering information section. as a result, toggling vset under default conditions has no affect. however, by re-programming one or more regulator's vset0[ ] and/or vset1[ ] registers, one can easily toggle these regulators' output voltages between two sets of voltages, such as to implement 'normal' and 'standby' modes in a system utilizing the act8810 to implement an advanced power management architecture. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dcs exhibit discontinuous input current, so the input capacitors should be placed as functional description cont?d ? ? ? ? ? ? ? ? ? = 1 v v r r fbx outx 2 fb 1 fb (1) r fb1 r fb2 outx act8810 fbx c ff
step-down dc/dc converters act8810 rev 9, 15-nov-12 innovative power tm - 30 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. close as possible to the ic, and avoiding the use of vias if possible. the inducto r, input filter capacitor, and output filter capacitor s hould be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator?s power loop should be connected at a single point in a star- ground configuration, and this point should be connected to the backside ground plane with multiple vias. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside gr ound plane using multiple vias to achieve low electric al and thermal resistance. functional description cont?d
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 31 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. (v inl = 3.6v, c out4 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 2.6 5.5 v inl uvlo threshold v inl input rising 2.4 2.5 2.6 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -2% v nom4 +2% v t a = -40c to 85c -3% v nom4 +3% line regulation error v inl = max(v out5 + 0.5v, 3.6v) to 5.5v 0 %/v load regulation error i out5 = 1ma to 360ma -0.07 mv/ma power supply rejection ratio f = 1khz, i out4 = 360ma, c out4 = 1f 70 db f = 10khz, i out4 = 360ma, c out4 = 1f 60 supply current per output regulator enabled 35 a regulator disabled 0 dropout voltage 3 i out4 = 160ma, v out4 > 3.1v 100 200 mv output current 360 ma current limit v out4 = 95% of regulation voltage 400 internal soft-start 100 s power good flag high threshold v out4 , hysteresis = -2% 88 % output noise c out4 = 10f, f = 10hz to 100khz 40 v rms stable c out4 range 1 20 f discharge resistor in shutdown ldo disabled, dis4[ ] = [1] 1000 ? : v nom4 refers to the nominal output voltage level for v out4 as defined by the ordering information section. : psrr is lower with v set < 1.25v 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) : ldo current limit is defined as the output current at which t he output voltage drops to 95% of the respective regulation volt age. un- der heavy overload conditions the output current limit folds back by 40% (typ) electrical characteristics (reg4)
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 32 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. parameter test conditions min typ max unit inl operating voltage range 2.6 5.5 v inl uvlo threshold v inl input rising 2.4 2.5 2.6 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -2% v nom5 +2% v t a = -40c to 85c -3% v nom5 +3% line regulation error v inl = max(v out5 + 0.5v, 3.6v) to 5.5v 0 %/v load regulation error i out5 = 1ma to 360ma -0.07 mv/ma power supply rejection ratio f = 1khz, i out5 = 360ma, c out5 = 1f 70 db f = 10khz, i out5 = 360ma, c out5 = 1f 60 supply current per output regulator enabled 35 a regulator disabled 0 dropout voltage 3 i out5 = 160ma, v out5 > 3.1v 100 200 mv output current 360 ma current limit v out5 = 95% of regulation voltage 400 ma internal soft-start 100 s output noise c out5 = 10f, f = 10hz to 100khz 40 v rms stable c out5 range 1 20 f discharge resistor in shutdown ldo disabled, dis5[ ] = [1] 1000 ? electrical characteristics (reg5) (v inl = 3.6v, c out5 = 1f, t a = 25c, unless otherwise specified.) : v nom5 refers to the nominal output voltage level for v out5 as defined by the ordering information section. : psrr is lower with v set < 1.25v 3 : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) : ldo current limit is defined as the output current at which t he output voltage drops to 95% of the respective regulation volt age. un- der heavy overload conditions the output current limit folds back by 40% (typ)
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 33 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. 0 typical performanc e characteristics (act8810qj3eb, v vsys = 5v, t a = 25c, unless otherwise specified.) output regulation voltage vs. load current output regulation voltage (%) load current (ma) 1.5 act8810-012 1.0 0.5 0.0 -0.5 -1.0 output voltage deviation vs. temperature output voltage deviation (%) temperature (c) -40 85 act8810-014 10 35 60 ldo output voltage noise ch1 ch1: v outx , 200v/div (ac coupled) time: 200ms/div c ref = 10nf 40 80 120 160 200 240 280 320 360 -0.5 2.00 1.50 1.00 0.50 act8810-015 -15 i load = 0ma 0.00 -1.5 act8810-016 region of stable c out esr vs. output current 1 0.1 0.01 0 50 100 150 200 250 esr ( ? ) 300 360 output current (ma) stable esr dropout voltage (mv) output current (ma) dropout voltage vs. output current act8810-013 200 50 0 150 100 200 175 225 150 125 100 75 50 25 0 250 300 360 reg4, reg5 3.1v 3.3v 3.6v
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 34 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions note: see table 1 for default register settings. table 13: reg45 control register map address data d7 d6 d5 d4 d3 d2 d1 d0 40h dis4 r on4 vset4 41h dis5 r on5 vset5 43h r r r r r r nfltmsk ok address name bit access fu nction description 40h vset4 [4:0] r/w reg4 output voltage selection see table 15 40h on4 [5] r/w reg4 enable 0 reg4 disable 1 reg4 enable 40h [6] r read only 40h dis4 [7] r/w reg4 discharge enable 0 discharge disable 1 discharge enable 41h vset5 [4:0] r/w reg5 output voltage selection see table 15 41h on5 [5] r/w reg5 enable 0 reg5 disable 1 reg5 enable 41h [6] r read only 41h dis5 [7] r/w reg5 discharge enable 0 discharge disable 1 discharge enable 43h ok [0] r reg4 power-ok 0 output is not ok 1 output is ok nfltmsk [1] r/w reg4 output voltage fault mask option 0 masked 1 not mask 43h [7:2] r read only 43h table 14: reg45 control register bit descriptions r: read-only bits. default values may vary.
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 35 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions cont?d table 15: reg45/vsetx[ ] output voltage setting reg45cfg/vsetx[2:0] reg45cfg/vsetx[4:3] 00 01 10 11 000 0.90 1.45 1.90 2.75 001 1.00 1.50 2.00 2.80 010 1.10 1.55 2.10 2.85 011 1.20 1.60 2.20 2.90 100 1.25 1.70 2.40 3.00 101 1.30 1.75 2.50 3.10 110 1.35 1.80 2.60 3.20 111 1.40 1.85 2.70 3.30
low-dropout line ar regulators act8810 rev 9, 15-nov-12 innovative power tm - 36 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description general description reg4 and reg5 are low-noise, low-dropout linear regulators (ldos) that are optimized for low noise and high-psrr operation, achieving more than 60db psrr at frequencies up to 10khz. ldo output voltage programming all ldos feature independently-programmable output voltages that are set via the i 2 c serial interface, increasing the act8810?s flexibility while reducing total solution size and cost. set the output voltage by writing to the reg45cfg/vsetx[ ] registers. output current capability reg4 and reg5 each supply an output current of 360ma. excellent performance is achieved over this load current range. output current limit in order to ensure safe operation under over-load conditions, each ldo features current-limit circuitry with current fold-back. the current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. for additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 40% under extreme overload conditions. enabling and disabling the ldos all ldos feature independent enable/disable control via the i 2 c serial interface. independently enable or disable each output by writing to the appropriate reg45cfg/onx[ ] bit. in addition reg4 or reg5 may be enable when npbin is pushed low via 100k ? resistance. it depends on sequence is set. see the control sequence section for more information. power-ok reg4 features power-ok st atus bit that can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power-ok threshold, typically 12% below the programmed regulation voltage, the corresponding reg45cfg/ok[ ] will clear to 0. reference bypass pin the act8810 contains a reference bypass pin which filters noise from the reference, providing a low noise voltage reference to the ldos. bypass refbp to ga with a 0.01 f ceramic capacitor. optional ldo output discharge each of the act8810?s ldos features an optional, independent output voltage discharge feature. when this feature is enabled, the ldo output is discharged to ground through a 1k ? resistance when the ldo is shutdown. this feature may be enabled or disabled via the i 2 c interface by writing to the reg45cfg/disx[ ] bits. output capacitor selection reg4 and reg5 each require only a small ceramic capacitor for stability. for best performance, each output capacitor should be connected directly between the outx and ga pins as possible, with a short and direct connection. to ensure best performance for the device, the output capacitor should have a minimum capacitance of 1 f, and esr value between 10m ? and 200m ? . high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. pcb layout considerations the act8810?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configurati on for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a filtered reference noise, and internally has a direct connection to the linear regulator controller. any noise injected onto refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ldo output capacitors, the refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of vias whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible.
rtc low-dropout linear regulator act8810 rev 9, 15-nov-12 innovative power tm - 37 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. electrical characteristics (reg6) (t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit input supply range 2.6 5.5 v output voltage accuracy t a = 25c -2% v nom6 +2% v t a = -40c to 85c -3% v nom6 +3% line regulation error v inl = v out6 + 0.5v to v inl = 5.5v 0.1 %/v load regulation error i out6 = 0ma to 30ma -0.01 %/ma input supply current on1 = on2 = on3 = ga 6 12 a dropout voltage i out6 = 10ma 35 70 mv output current 30 ma current limit 3 v out6 = 95% of regulation voltage 45 ma stable c out6 range 1 20 f : v nom6 refers to the nominal output voltage level for v out6 as defined by the ordering information section. : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) 3 : ldo current limit is defined as the output current at which t he output voltage drops to 95% of the respective regulation volt age.
rtc low-dropout linear regulator act8810 rev 9, 15-nov-12 innovative power tm - 38 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. register descriptions note: see table 1 for default register settings. table 16: reg6 control register map address data d7 d6 d5 d4 d3 d2 d1 d0 42h r r r vset6 address name bit access fu nction description 42h vset6 [4:0] r/w reg6 output voltage selection see table 18 42h [7:5] r read only table 17: reg6 control register bit descriptions r: read-only bits. default values may vary. table 18: reg6/vsetx[ ] output voltage setting reg6cfg/vsetx[2:0] reg6cfg/vsetx[4:3] 00 01 10 11 000 0.90 1.45 1.90 2.75 001 1.00 1.50 2.00 2.80 010 1.10 1.55 2.10 2.85 011 1.20 1.60 2.20 2.90 100 1.25 1.70 2.40 3.00 101 1.30 1.75 2.50 3.10 110 1.35 1.80 2.60 3.20 111 1.40 1.85 2.70 3.30
rtc low-dropout linear regulator act8810 rev 9, 15-nov-12 innovative power tm - 39 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. general description reg6 is an always-on, low-dropout linear regulator (ldo) that is optimized for rtc and backup-battery applications. reg6 features low-quiescent supply current, current-limit protection, and reverse-current protection, and is ideally suited for always-on power supply applications, such as for a real-time clock, or as a backup-battery or super-cap charger. output voltage by default, reg6's output voltage is as defined in the ordering information section. however, this voltage may be programmed by writing to the reg6cfg/vsetx[ ] register via the i 2 c interface. reverse-current protection reg6 features internal circuitry that limits the reverse supply current to less than 1a when the input voltage falls below the output voltage, as can be encountered in backup-battery charging applications. reg6's internal circuitry monitors the input and the output, and disconnects internal circuitry and parasitic diodes when the input voltage falls below the output voltage, greatly minimizing backup battery discharge. typical application voltage regulators reg6 is ideally suited for always-on voltage- regulation applications, such as for real-time clock and memory keep-alive applications. this regulator requires only a small ceramic capacitor with a minimum capacitance of 1 f for stability. for best performance, the output capacitor should be connected directly between the output and ga, with a short and direct connection. figure 9: typical application of rtc ldo backup battery charging reg6 features a const ant current-limit, which protects the ic under output short-circuit conditions as well as provides a constant charge current, when operating as a backup battery charger. as shown in figure 10, reg6 features a cc/cv output characteristic, regulating its output voltage for load currents up to 30ma, and regulating output current when the load exceeds (typically) 60ma. figure 10: reg6 output voltage functional description output voltage (v) act8810-017 4 3 2 1 0 reg6 output voltage vs. load current constant voltage region constant current region load current (ma) 20 0 40 60 80 100 act8810 rtc supper cap or back-up battery out6
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 40 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. electrical characteristics (v chg_in = 5v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit activepath chg_in operating voltage range 4.35 6.0 v chg_in uvlo threshold chg_in voltage rising 3.6 3.8 4.0 v chg_in uvlo hysteresis chg_i n voltage falling 0.8 v chg_in ovp threshold chg_in vo ltage falling 6.0 6.5 7.0 v chg_in ovp hysteresis chg_in voltage rising 350 mv chg_in supply current v chg_in < v uvlo 20 a v chg_in < v bat + 120mv, v chg_in > v uvlo 50 120 200 a v chg_in > v bat + 120mv, v chg_in > v uvlo charger disabled, i sys = 0ma 1.8 ma chg_in to vsys on-resistance i vsys = 100ma 0.4 0.6 ? chg_in to vsys current limit acin = vsys 1.5 2 3 a acin = ga, chglev = ga 85 95 105 ma acin = ga, chglev = vsys 400 450 500 vsys and dccc regulation vsys regulated voltage i vsys = 10ma 4.4 4.6 4.8 v dccc pull-up current v chg_in > v bat + 120mv, hysteresis = 50mv 92 100 108 a nstatx output nstatx sink current v nstatx = 2v 3 5 7 ma nstatx output low voltage i nstatx = 1ma 0.4 v nstatx leakage current v nstatx = 4.2v 1 a acin and chglev inputs chglev logic high input voltage 1.4 v chglev logic low input voltage 0.4 v chglev leakage current v chglev = 4.2v 1 a acin logic high input voltage 1.4 v acin logic low input voltage 0.4 v acin leakage current v acin = 4.2v 1 a temperature sense comparator th pull-up current v chg_in > v bat + 120mv, hysteresis = 50mv 92 100 108 a v th upper temperature voltage threshold (v thh ) hot detect ntc thermistor 0.485 0.500 0.525 v v th lower temperature voltage threshold (v thl ) cold detect ntc thermistor 2.47 2.52 2.57 v v th hysteresis upper and lower 30 mv
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 41 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. electrical characteristics cont?d (v chg_in = 5v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit charger bat reverse leakage current v chg_in = 0v, v bat = 4.2v, i vsys = 0ma 5 a bat to vsys on-resistance 80 m ? iset pin voltage fast charge 1.02 v precondition 0.12 charge termination voltage t a = -20c to 70c 4.179 4.2 4.221 v t a = -40c to 85c 4.170 4.230 charge current v bat = 3.5v, r iset = 1.2k ? acin = vsys, chglev = vsys -10% iset 1 +10% ma acin = vsys, chglev = ga -16% 50%iset +16% acin = ga, chglev = vsys -10% smallest (450ma or iset) +10% acin = ga, chglev = ga -10% smallest (90ma or iset) +10% precondition charge current v bat = 2.5v, r iset = 1.2k ? acin = vsys, chglev = vsys 12%iset ma acin = vsys, chglev = ga 12%iset acin = ga, chglev = vsys 12%iset acin = ga, chglev = ga smallest (90ma or 12%iset) precondition threshold voltage v bat voltage rising 2.75 2.85 2.95 v precondition threshold hysteresis v bat voltage falling 100 mv end-of-charge current threshold v bat = 4.2v, r iset = 1.2k ? acin = vsys, chglev = vsys 10%iset ma acin = vsys, chglev = ga 10%iset acin = ga, chglev = vsys 5%iset acin = ga, chglev = ga 5%iset charge restart threshold v set - v bat , v bat falling 150 170 190 mv fast charge safety timer t normal r btr = 62 k ? 3 hr precondition safety timer t precondition r btr = 62 k ? 1 2 hr thermal regulation thermal regulation threshold 100 145 c : iset (ma) = k iset 1v/(r iset (k ? ) +0.031) where k iset = 628 2 : t precondition = t normal / 3 (typ)
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 42 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. typical performanc e characteristics (v chg_in = 5v, r dccc = 20k, r iset = 680 ? , t a = 25c, unless otherwise specified.) act8810-018 sys current (ma) 0 1000 2000 3000 act8810-019 4.25 4.15 4.05 3.95 3.85 3.75 sys voltage (v) i sys = 10ma v bat = 4.2v sys output voltage vs. chg_in voltage sys voltage vs. sys current 4.8 4.6 4.5 4.4 4.3 4.2 4.1 4.0 4.7 sys voltage (v) chg_in voltage (v) 0 2 4 6 8 10 12 14 battery voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 act8810-020 charger current vs. battery voltage (usb mode) charger current (ma) chg_in = 5v i sys = 0ma 100ma usb 100 80 60 40 20 0 v bat falling v bat rising battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 act8810-021 charger current vs. battery voltage (usb mode) 450 400 350 300 250 200 150 100 50 0 500 charger current (ma) act8810-022 charger current vs. battery voltage (ac mode) charger current (ma) 900 800 700 600 500 400 300 200 100 0 battery voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 battery voltage falling battery voltage rising ambient temperature (c) -40 -20 0 20 40 60 80 100 120 140 act8810-023 fast charge current vs. ambient temperature fast charger current (ma) acin, chglev = 11 acin, chglev = 10 acin, chglev = 01 acin, chglev = 00 1200 1000 800 600 400 200 0 chg_in = 5v i sys = 0ma 500ma usb battery voltage falling battery voltage rising i sys = 0ma
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 43 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. typical performance ch aracteristics cont?d vac applied, chglev = low vac applied, chglev = high vac removed, chglev = low vac removed, chglev = high act8810-024 act8810-025 act8810-026 act8810-027 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1: v usb , 2.00v/div ch2: v chg_in , 2.00v/div ch3: i bat , 500ma/div ch4: v vac , 2.00v/div time: 400s/div ch1: v usb , 2.00v/div ch2: v chg_in , 2.00v/div ch3: i bat , 500ma/div ch4: v vac , 2.00v/div time: 400s/div ch1: v usb , 2.00v/div ch2: v chg_in , 2.00v/div ch3: i bat , 500ma/div ch4: v vac , 2.00v/div time: 400s/div ch1: v usb , 2.00v/div ch2: v chg_in , 2.00v/div ch3: i bat , 500ma/div ch4: v vac , 2.00v/div time: 400s/div 100ma 450ma 100ma 450ma battery voltage (v) 0 1 2 4 3 5 act8810-028 10 8 6 4 2 0 battery leakage current (a) battery leakage current vs. battery voltage no chg_in chglev = 0 (v chg_in = 5v, r dccc = 20k, r iset = 680 ? , t a = 25c, unless otherwise specified.)
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 44 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description general description the act8810 incorporates active-semi's patent- pending activepath architecture. activepath is a complete battery-charging and system power- management solution for portable hand-held equipment. this circuitry performs a variety of advanced battery-management functions, including automatic selection of the best available input supply, current-managem ent to ensure system power availability, and a complete, high-accuracy (0.5%), thermally regul ated, full-featured single- cell linear li+ charger with an integrated 12v power mosfet. activepath architecture active-semi's patent-pending activepath architecture performs three important functions: 1) input protection, 2) system configuration optimization, and 3) battery-management input protection at the input of the act8810's activepath circuit is an internal, low-dropout li near regulator (ldo) that regulates the system voltage (vsys). this ldo features a 12v power mosfet, allowing the activepath system to withstand input voltages of up to 12v, and additionally includes a variety of other protection features, including current limit protection and input over-voltage protection. the activepath circuitry provides a very simple means of implementing a solution that safely operates within the current-capability limitations of a usb port while taking advantage of the high output- current capability of an ac adapter, when available. activepath limits the total cu rrent drawn from the input supply to a value set by the acin input; when acin is driven to a logic-low activepath operates in ?usb mode? and limits the current to either 500ma (when chglev is driven to a logic-high) or to 100ma (when chglev is driven to a logic-low), and when acin is driven to a logic-high activepath operates in ?ac-mode? and limits the input current to 2a. in either case, activepath's dccc circuitry, described below, allows the input overload protection to be adjusted to accommodate a wide range of input supplies. system configurat ion optimization activepath circuitry automatica lly detects the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. if the input supply is present, activepath powers the system in parallel with charging the battery, so that system power and charge current can be independently managed to satisfy all system power requirements. this allows the battery to charge as quickly as possible, while ensuring that the total system current does not exceed the capability of the input supply. if the input supply is not present, however, then activepath automatically configures the system to draw power from the battery. finally, if the input is present and the system current requirement exceeds the capability of the input supply, such as under momentary peak-power consumption conditions, activepath automatically configures itself for maximum power capability by drawing system power from both the battery and the input supply. battery management activepath includes a full-featured battery charger for single-cell li-based batteries. this charger is a full-featured, intelligent, linear-mode, single-cell charger for lithium-based cells, and was designed specifically to provide a complete charging solution with minimum system design effort. the core of the activepath's charger is a cc/cv (constant-current/constant-voltage), linear-mode charge controller. this controller incorporates current and voltage sense circuitry, an internal 80m ? power mosfet, a full-featured state- machine that implements charge control and safety features, and circuitry that eliminates the reverse- blocking diode required by conventional charger designs. this charger also features thermal-regulation circuitry that protects it against excessive junction temperature, allowing the fastest possible charging times, as well as proprietary input protection circuitry that makes the charger robust against input voltage transients that can damage other chargers. the charge termination voltage is highly accurate (0.5%), and features a se lection of charge safety timeout periods that pr otect the system from operation with damaged ce lls. other features include pin-programmable fast-charge current and
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 45 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. acin chglev charge current i chg (ma) precondition charge current i chg (ma) 0 0 90ma or iset (smallest one) 90ma or 12%iset (smallest one) 0 1 450ma or iset (smallest one) 12% iset 1 0 50% iset 12% iset 1 1 iset 12% iset functional description cont?d two current-limited nstat0 and nstat1 outputs that can directly drive le d indicators or provide a logic-level status signal to the host microprocessor . dynamic charge current control (dccc) the act8810's activepath charger features dynamic charge current cont rol (dccc) circuitry, which continuously monitors the input supply to prevent input overload conditions. dccc reduces the charge current when the vsys voltage decreases to v dccc and stops charging when vsys drops below v dccc by 1.5% (typical). the dccc voltage threshold is programmed by connecting a resistor from dccc to ga according to the following equation: v dccc = 2 (i dccc r dccc ) (2) where r dccc is the value of the external resistor, and i dccc (100a typical) is the value of the current sourced from dccc. given the tolerances of the r dccc and i dccc , the dccc voltage threshold should be programmed to be no less than 3.3v to prevent triggering the uvlo, and to be no larger than 4.4v to prevent engaging dccc prematurely. a 19.1k (1%), or 18.7k (1%) resistor for r dccc is recommended. charger current programming the act8810's activepath charger features a flexible charge current-programming scheme that combines the convenience of internal charge current programming with the flexibility of resistor based charge current programming. current limits and charge current programming are managed as a function of the acin and chglev pins, in combination with r iset , the resistance connected to the iset pin. acin and chglev inputs acin is a logic input that configures the current-limit of activepath's linear regulator as well as that of the battery charger. acin features a precise 1.25v logic threshold, so that the input voltage detection threshold may be adjusted with a simple resistive voltage divider. this input also allows a simple, low- cost dual-input charger switch to be implemented with just a few, low-cost components. when acin is driven to a logic high, the activepath operates in ?ac-mode? and the charger charges at the current programmed by r iset , iset (ma) = k iset 1v/(r iset (k ? ) +0.031) (3) where k iset = 628 when chglev is driven to a logic high, and k iset = 314 when chglev is driven to a logic low. when acin is driven to a logic-low, the activepath circuitry operates in ?usb-mode?, which enforces a maximum charge current setting of 500ma, if chglev is driven to a logic-high, or 100ma, if chglev is driven to a logic-low. the act8810's charge current settings are summarized in the table below: table 19: acin and chglev inputs table note that the actual charging current may be limited to a current that is lowe r than the programmed fast charge current due to the act8810?s internal thermal regulation loop. see the thermal regulation and protection section for more information. battery temperature monitoring the act8810 continuously monitors the temperature of the batte ry pack by sensing the resistance of its thermistor, and suspends charging if the temperature of the battery pack exceeds the safety limits. in a typical application, shown in figure 11, the th pin is connected to the battery pack's thermistor input. the act8810 injects a 100a current out of the th pin into the thermistor, so that the thermistor resistance is monitored by comparing the voltage at th to the internal v thh and v thl thresholds of 0.5v and 2.5v, respectively. when v th > v thl or v th < v thh charging and the charge timers are suspended. when v th returns to the normal range, charging and the
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 46 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description cont?d charge timers resume. the net resistance from th to ga required to cross the threshold is given by: 100a r nom k hot = 0.5v r nom k hot = 5k ? 100a r nom k cold = 2.5v r nom k cold = 25k ? where r nom is the nominal thermistor resistance at room temperature, and k hot and k cold are the ratios of the thermistor's resist ance at the desired hot and cold thresholds, respectively. figure 11: simple configuration design procedure when designing with thermi stors it is important to keep in mind that their nonlinear behavior typically allows one to directly control no more than one threshold at a time. as a result, the design procedure can change depending on which threshold is most critical for a given application. most application requirements can be solved using one of three cases, 1) simple solution 2) fix v thh , accept the resulting v thl 3) fix v thl , accept the resulting v thh the act8810 was designed to achieve an operating temperature range that is suitable for most applications with very little design effort. the simple solution is often found to provide reasonable results and should always be used first, then the design procedure may proceed to one of the other solutions if necessary. in each design example, we refer to the vishay nths series of ntcs, and more specifically those which follow a "curve 2" characteristic. for more information on these ntcs, as well as access to the resistance/temperature characteristic tables referred to in the example, please refer to the vishay website at http://www.vishay.com/thermistors. simple solution the act8810 was designed to accommodate most requirements with very little design effort, but also provides flexibility when additional control over a design is required. initial thermistor selection is accomplished by choosin g one that best meets the following requirements: r nom = 5k ? /k hot , and r nom = 25k ? /k cold where k hot and k cold for a given thermistor can be found on its characteristic tables. taking a 0c to 40c application using a "curve 2" ntc for this example, from the characteristic tables one finds that k hot and k cold are 0.5758 and 2.816, respectively, and the r nom that most closely satisfies these requirem ents is therefore around 8.8k ? . selecting 10k ? as the nearest standard value, calculate k cold and k hot as: k cold = v thl /(i th r nom ) = 2.5v/(100a 10k ? ) = 2.5 k hot = v thh /(i th r nom ) = 0.5v/(100a 10k ? ) = 0.5 identifying these values on the curve 2 characteristic tables indi cates that the resulting operating temperature range is 2c to 44c, vs. the design goal of 0c to 40c. this example demonstrates that one can satisfy common operating temperature ranges with very little design effort. fix v thh for demonstration purposes, supposing that we had selected the next clos est standard thermistor value of 6.8k ? in the example above, we would have obtained the following results: k cold = v thl /(i th r nom ) = 2.5v/(100a 6.8k ? ) = 3.67 k hot = v thh /(i th r nom ) = 0.5v/(100a 6.8k ? ) = 0.74 which, according to the characteristic tables would have resulted in an operating temperature range of -6c to 33c vs. the design goal of 0c to 40c.
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 47 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description cont?d in this case, one can add resistance in series with the thermistor to shift the range upwards, using the following equation: (v thh /i th ) = k hot (@40c) r nom + r r = (v thh /i th ) - k hot (@40c) r nom r = (2.5v/100a) - 0.5758 6.8k ? finally, r = 5k ? - 3.9k ? = 1.1k ? this result shows that adding 1.1k ? in series with the thermistor sets the net resistance from th to g to be 0.5v at 40c, satisfying v thh at the correct temperature. adding this resistance, however, also impacts the lower temperature limit as follows: v thl /i th = k cold (@tc) r nom + r k cold (@tc) = (v thl /i th ) - r)/r nom finally, k cold (@tc) = (25k ? - 1.1k ? )/6.8k ? = 3.51 reviewing the characteristic curves, the lower threshold is found to move to -5c, a change of only 1c. as a result, the system satisfies the upper threshold of 40c with an operating temperature range of -5c to 40c, vs. our design target of 0c to 40c. it is informative to highlight that due to the ntc behavior of the thermi stor, the relative impact on the lower threshold is significantly smaller than the impact on the upper threshold. fix v thl following the same example as above, the "unadjusted" results yield an operating temperature range of -6c to 33c vs. the design goal of 0c to 40c. in applications that favor v thl over v thh , however, one can control the voltage present at th at low temperatures by connecting a resistor in parallel with i th . the desired resistance can be found using the following equation: (i th + (v chg_in - v thl )/r) k cold (@0c) r nom = v thl rearranging yields r = (v chg_in - v thl )/(v thl /(k cold (@0c) r nom ) - i th ) r = (5v - 2.5v)/(2.5v/(2.816 6.8k ? ) - 100a) r = 82k ? adding 82k ? in parallel with the current source increases the net current fl owing into the thermistor, thus increasing the voltage at th. adding this resistance, however, also impacts the upper temperature limit: v thh = (i th + (v chg_in - v thh )/r) k hot (@40c) r nom rearranging yields, k hot (@tc) = v thh /(r nom (i th + (v chg_in - v thh )/r)) k hot (@tc) = 0.5v/(6.8k ? (100a + (5v - 0.5v)/82k ? )) = 0.4748 reviewing the characteristic curves, the upper threshold is found to move to 45c, a change of figure 12: fix v thh configuration figure 13: fix v thl configuration
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 48 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. state nstat0 nstat1 precondition on on fast-charge, top-off on off end-of-charge off on fault, suspend off off functional description cont?d about 14c. adding the parallel resistance has allowed us to achieve our desired lower threshold of 0c with an operating temperature range of 0c to 45c, vs. our design target of 0c to 40c. thermal regulation the act8810's activepath charger features an internal thermal regulation loop that reduces the charging current as necessary to ensure that the die temperature does not rise beyond the thermal regulation threshold of 110c. this feature protects the against excessive junction temperature and makes the device more accommodating to aggressive thermal designs. note, however, that attention to good thermal designs is required to achieve the fastest possible charge time by maximizing charge current. in order to account for the reduced charge current resulting from operation in thermal regulation mode, the charge timeout periods are extended proportionally to the reduction in charge current. charging safety timers the act8810 features a safety timer that is programmable via an external resistor (r btr ) connected from btr to ga. the timeout period is calculated as show in figure 14. if the act8810 detects that the charger remains in precondition for longer than the precondition time out period (which determined as t chg /3), the act8810 turns off the charger and generate a fault to ensure prevent charging a bad cell. charging status indication the act8810 provides two charge-status outputs, nstat0 and nstat1, which indicate charge status as defined in table 20. nstat0 and nstat1 are open-drain outputs with internal 5ma current limits, which sink current when asserted and are high-z otherwise, and are capable of directly driving leds without the need of current-limiting resistors or other external circuitry. to drive an led, simply connect the led between each pin and an appropriate supply (typic ally vsys). for a logic level indication, simply connect a resistor from each output to a appropriate voltage supply. table 20: charging status indication table input supply detection the act8810's activepath charger is capable of withstanding voltages of up to 12v, protecting the system from fault conditio ns such as input voltage transients or application of an incorrect input supply. although the act8810 can withstand a wide range of input voltages, valid input voltages for charging must be greater than the under-voltage lockout voltage (uvlo) and the over-voltage protection (ovp) thresholds, as described below. under voltage lock output (uvlo) whenever the input voltage applied to chg_in falls below 3.0v (typ), an input under-voltage condition is detected and the charger is disabled. once an input under-voltage condition is detected, the input must exceed the under-voltage threshold by at least 800mv for charging to resume. over voltage protection (ovp) if the charger detects that the voltage applied to chg_in exceeds 6.5v (typ), an over-voltage condition is detected and the charger is disabled. once an input over-voltage condition is detected, the input must fall below the ovp threshold by at least 350mv for charging to resume. reverse leakage current the act8810's activepath charger includes internal circuitry that eliminates the need for blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. when the voltage at chg_in falls below v bat , the charger automatically reconfigures its power switch to minimize current drain from the battery.
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 49 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. figure 15: typical li+ charge profile and act8810 charge states figure 14: r btr (k ? ) 20 30 40 50 60 70 80 90 100 110 t normal vs. r btr t normal (min) 275 225 175 125 75 a: precondition state b: fast-charge state c: top-off state d: end-of-charge state
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 50 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. figure 16: charger state diagram suspend precondition fast-charge end-of-charge battery removed or (v chgin < v bat ) or (v chgin v ovp ) battery replaced and (v chgin > v bat ) and (v chgin >v chgin uvlo) and (v chgin < v ovp ) v bat > 2.85v v bat = v term temp-fault top-off i bat < i eoc or t > t normal temp ok any state temp not ok timeout-fault t > t precondition t > t normal
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 51 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description cont?d charger state-machine precondition state a new charging cycle begins with the precondition state, and operation continues in this state until v bat exceeds the precondition threshold voltage of 2.85v (typ). when operating in precondition state, the cell is charged at a reduced current, 12% of the programmed maximum fast-charge constant current, iset. once v bat reaches the precondition threshold voltage the state machine jumps to the fast-charge state. if v bat does not reach the precondition threshold voltage before the precondition timeout period t precondition expires, then a damaged cell is detected and the state machine jumps to the timeout-fault state. for the precondition timeout period, see the charging safety timers section for more information. fast-charge state in fast-charge state, the act8810 charges at the current programmed by r iset (see the current limits and charge current programming section for more information). during a normal charge cycle fast-charge continues in cc mode until v bat reaches the charge termination voltage (v term ), at which point the act8810 jumps to the top-off state. if v bat does not reach v term before the total time out period expires then state-machine will jump to the end-of-charge (eoc) state and will re- initiate a new charge cycle after 2-4ms ?relax?. top-off state in the top-off state, the cell charges in constant voltage (cv) mode. in cv mode operation, the charger regulates its output voltage to the 4.20v (typ) charge termination voltage, and the charge current is naturally reduced as the cell approaches full charge. charging cont inues until the charge current drops to end-of-charge current threshold, at which point the state machine jumps to the end-of-charge (eoc ) state. if the state- machine does not jump out of the top-off state before the total-charge tim eout period expires, the state machine jumps to the eoc state and will re- initiate a new charge cycle if v bat falls below termination voltage 170mv (typ). for more information about the charge safety timers, see the charging safety times section. end-of-charge state in the end-of-charge (eoc) state, the act8810 presents a high-impedance to the battery, allowing the cell to ?relax? and minimizes battery leakage current. the act8810 continues to monitor the cell voltage, so that it can re -initiate charging cycles when v bat drops to 170mv (typ) below the charge termination voltage. suspend state in the suspend state, act8810 disables the charger but keeps other circuiting functional. upon exiting the suspend state, the charge timer is reset and the state machine jumps to precondition state. chg_in bypass capacitor selection chg_in is the power input for the act8810 battery charger. the battery charger is automatically enabled whenever a valid voltage is present on chg_in. in most applications, chg_in is connected to either a wall adapter or usb port. under normal operation, the input of the charger will often be ?hot-plugged? directly to a powered usb or wall adapter cable, and supply voltage ringing and overshoot may appear at the chg_in pin. in most applications a high quality capacitor connected from chg_in to ga, placed as close as possible to the ic, is sufficient to absorb the energy. wall-adapter powered applicat ions provide flexibility in input capacitor selection, but the usb specification presents limitations to input capacitance selection. in order to meet both the usb 2.0 and usb otg (on the go) specifications while avoiding usb supply under-voltage conditions resulting from the current limit slew rate (100ma/s) limitations of the usb bus, the chg_in bypass capacitance value must to be between 4.7f and 10f for the act8810. ceramic capacitors are often preferred for bypassing applications due to their small size and good surge current ratings, but care must be taken in applications that can encounter hot plug conditions as their very low esr, in combination with the inductance of t he cable, can create a high- q filter that induces excessive ringing at the chg_in pin. this ringing can couple to the output and be mistaken as loop instability, or the ringing may be large enough to damage the input itself.
activepath tm charger act8810 rev 9, 15-nov-12 innovative power tm - 52 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. functional description cont?d although the chg_in pin is designed for maximum robustness and an absolute maximum voltage rating of 14v for transients, attention must be given to bypass techniques to ensure safe operation. as a result, design of the chg_in bypass must take care to ?de-q? the filter. this can be accomplished by connecting a 1 ? resistor in series with a ceramic capacitor (as shown in figure 17), or by using a tantalum or el ectrolytic capacitor to utilize it?s higher esr to dampen the ringing. for additional protection in extreme situations, zener diodes with 12v clamp voltages may also be used. in any case, it is always critical to evaluate voltage transients at the act8810 chg_in pin with an oscilloscope to ensure safe operation. figure 17: chg_in bypass options for usb or wall adaptor supplies
act8810 rev 9, 15-nov-12 package outline and dimensions innovative power tm - 53 - www.active-semi.com copyright ? 2012 active-semi, inc. activepmu tm and activepath tm are trademarks of active-semi. i 2 c tm is a trademark of nxp. package outline tqfn55-40 package outline and dimensions symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.200 ref 0.008 ref a2 0.000 0.050 0.000 0.002 b 0.150 0.250 0.006 0.010 d 4.900 5.100 0.193 0.201 e 4.900 5.100 0.193 0.201 d2 3.450 3.750 0.136 0.148 e2 3.450 3.750 0.136 0.148 e 0.400 bsc 0.016 bsc l 0.300 0.500 0.012 0.020 r 0.300 0.012 active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . is a registered trademark of active-semi.
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